Senior Engineer ASIC (1734)
Hyderabad, India
Description:
Responsible for the design and implementation of ASIC logic blocks . Specific tasks will include
RTL design and implementation of logic blocks.
Collaboration with RTL, synthesis, STA engineers in timing closure and debug
Design floor planning, place and route, timing analysis and physical verification
Involvement in all aspects of area, power and performance optimization.
Experience: 5-10 years
Warm Regards,
Suresh Ediga
Mentorware India,
www.mentorware.com,
Dir: +918067135410
Hyderabad, India
Description:
Responsible for the design and implementation of ASIC logic blocks . Specific tasks will include
RTL design and implementation of logic blocks.
Collaboration with RTL, synthesis, STA engineers in timing closure and debug
Design floor planning, place and route, timing analysis and physical verification
Involvement in all aspects of area, power and performance optimization.
Experience: 5-10 years
Warm Regards,
Suresh Ediga
Mentorware India,
www.mentorware.com,
Dir: +918067135410
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